1. Field of the Invention
The invention relates to a memory device having a memory array and particularly to managing random defects in memory locations of the memory array of the memory device.
2. Description of the Prior Art
Memory arrays have a variety of applications nearly all of which require reliability of the memory locations of such arrays. However, as readily known in the industry, memory arrays, which are organized in rows and columns of memory cells, readily include defective memory cells, which are generally identified prior to the memory array leaving its place of manufacturing. These defects are characterized as “massive” defects and “random” defects. “Massive” defects generally refer to defects that render an entire row or column defective or that are greater than that which is statistically considered random defects, whereas “random” defects appear more randomly in memory cells with no particular known pattern, such as in a row or a column of the memory array.
Both massive as well as random defects require management if the memory array is to be used in any practical memory application. The management of such defects is typically done by circuitry that controls the memory array. In the case of massive defects, an entire row or column is identified as defective and the defective row/column is replaced with a spare row/column by the circuitry that controls the memory array. This replacement prevents further use of the defective row and/or column for the entire remaining life time of the memory array. As can be appreciated, this type of defect management is not efficient for the case of random defects because an entire row or an entire column of memory cells is likely rendered unusable even though as few as one memory cell in the row or column may be defective.
Magnetic random access memory (MRAM) is a prime candidate for having random defects due to the non-uniform etching process and other processes employed during its manufacturing, MRAM memory cells typically experience random defects as opposed to massive defects or in some cases, in addition to massive defects. MRAM is quickly gaining wide popularity in various applications oftentimes replacing its current counterpart non-volatile memory and is anticipated to replace volatile memory in the near future. Therefore, the efficient management of random defects in a memory array that is made of MRAM memory cells is vital.
Techniques currently employed to manage random defects suffer from being costly due to their use of large memory. That is, circuits designed to manage defects map a defective address to a spare memory area, which is typically made of content addressable memory content-addressable memories (CAMs). CAMs operate by checking an incoming address, which is an input to the CAM, against its content and outputting a signal that reflects whether or not there is a match and an alternate address. Current defect management techniques use this as a way to identify a defective memory location in that defective addresses, as they are identified during manufacturing, are stored in the CAM so that when there is a match between the input of the CAM and the content of the CAM, a defective memory location is identified and an alternate address generated. When a cell being accessed is identified to be defective, the incoming address thereof is replaced with an alternate address associated with a spare cell. As can be appreciated, the shortcoming with this technique is that a large CAM is required, causing valuable real estate in addition to increased costs to the point of being impractical. In some current designs, two CAMs are employed, one for maintaining defective row addresses and another for maintaining defective column addresses, which is a costly solution for managing random defects as each random defect is mapped to a spare row (or column) which increases the memory array, among perhaps others.
Thus, the need arises for a memory device with an efficient and cost effective method and apparatus to manage random defects in its memory array.